久久中文视频-久久中文网-久久中文亚洲国产-久久中文字幕久久久久-亚洲狠狠成人综合网-亚洲狠狠婷婷综合久久久久


曙海教育集團論壇FPGA專區FPGA初中級 → FPGA 時鐘問題


  共有8402人關注過本帖樹形打印

主題:FPGA 時鐘問題

美女呀,離線,留言給我吧!
wangxinxin
  1樓 個性首頁 | 博客 | 信息 | 搜索 | 郵箱 | 主頁 | UC


加好友 發短信
等級:青蜂俠 帖子:1393 積分:14038 威望:0 精華:0 注冊:2010-11-12 11:08:23
FPGA 時鐘問題  發帖心情 Post By:2010-12-19 14:00:46

剛學不久~

我要做24H製的時鐘~但我一直DEBUG~一直用不出來~

Xilinx ISE 8.2i軟體~

請會的人幫我看一下哪出錯了~謝



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;


entity CLOCK_00_60 is

    Port ( CLK : in  STD_LOGIC;

           RESET : in  STD_LOGIC;

           ENABLE : out  STD_LOGIC_VECTOR (6 downto 0);

           SEGMENT : out  STD_LOGIC_VECTOR (6 downto 0));

end CLOCK_00_60;


architecture Behavioral of CLOCK_00_60 is

signal SCAN_CLK :STD_LOGIC;

signal COUNT_CLK :STD_LOGIC;

signal DECODE_BCD :STD_LOGIC_VECTOR (3 downto 0);

signal mineable :STD_LOGIC;

signal hreable :STD_LOGIC;

signal POSITION:STD_LOGIC_VECTOR (6 downto 0);

signal DIVIDER:STD_LOGIC_VECTOR (29 downto 1);

signal COUNT_BCD:STD_LOGIC_VECTOR (23 downto 0);


begin

-------------------------------------------------

process (CLK,RESET)

begin

if RESET = '0' then

 DIVIDER <= ( others => '0');

elsif CLK' event and CLK = '1' then

 DIVIDER <= DIVIDER + 1 ;

end if;

end process;

COUNT_CLK<=DIVIDER(24);

SCAN_CLK<=DIVIDER(15);

------------------------------------------------秒

process(RESET,SCAN_CLK)

begin

if RESET = '0' then

 COUNT_BCD <= ( others => '0');

elsif SCAN_CLK' event and SCAN_CLK = '1' then

 if   COUNT_BCD(3 downto 0)= x"9" then

    COUNT_BCD(3 downto 0)<= x"0";

    COUNT_BCD(7 downto 4)<= COUNT_BCD(7 downto 4)+1;

 else

   COUNT_BCD(3 downto 0)<= COUNT_BCD(3 downto 0)+1;

 end if;

end if;

end process;

mineable <= '1' when COUNT_BCD(7 downto 0) = x"59" else '0';

----------------------------------------------------------分


process(RESET,SCAN_CLK)

begin

if RESET = '0' then

 COUNT_BCD <= ( others => '0');

 if mineable = '1' then

elsif SCAN_CLK' event and SCAN_CLK = '1' then

 if   COUNT_BCD(11 downto 8)= x"9" then

    COUNT_BCD(11 downto 8)<= x"0";

    COUNT_BCD(15 downto 12)<= COUNT_BCD(15 downto 12)+1;

 else

   COUNT_BCD(11 downto 8)<= COUNT_BCD(11 downto 8)+1;

 end if;

end if;

end if;

end process;

hreable <= '1' when COUNT_BCD(15 downto 8) = x"59" else '0';

-------------------------------------------------------------時

process(RESET,SCAN_CLK)

begin

if RESET = '0' then

 COUNT_BCD <= ( others => '0');

  if mineable = '1' and hreable = '1' then

elsif SCAN_CLK' event and SCAN_CLK = '1' then

 if   COUNT_BCD(19 downto 16)= x"9" then

    COUNT_BCD(19 downto 16)<= x"0";

    COUNT_BCD(23 downto 20)<= COUNT_BCD(23 downto 20)+1;

  if   COUNT_BCD(19 downto 16)= x"2" then

   COUNT_BCD(23 downto 20)<= x"0";

 else

   COUNT_BCD(19 downto 16)<= COUNT_BCD(19 downto 16)+1;

  end if;

 end if;

  end if;

end if;

end process;



process(RESET,SCAN_CLK)

begin

if RESET = '0' then

 POSITION <= "1111110";

elsif SCAN_CLK' event and SCAN_CLK = '1' then

 POSITION<="111111"&POSITION(0);

end if;

end process;

ENABLE<=POSITION;

-----------------------------------------------------------

process(POSITION,SCAN_CLK)

begin

case POSITION is

 when "1111110" => DECODE_BCD <=COUNT_BCD(3 downto 0);    --秒

 when "1111101" => DECODE_BCD <=COUNT_BCD(7 downto 4);    --秒

 when "1111011" => DECODE_BCD <=COUNT_BCD(11 downto 8);   --分

 when "1110111" => DECODE_BCD <=COUNT_BCD(15 downto 12);   --分

   when "1101111" => DECODE_BCD <=COUNT_BCD(19 downto 16);   --時

   when "1011111" => DECODE_BCD <=COUNT_BCD(23 downto 20);   --時

 when others => null;

end case;

end process;

 

with DECODE_BCD Select

SEGMENT<= "1000000" when X"0",

  "1111001" when X"1",

  "0100100" when X"2",

  "0110000" when X"3",

  "0011001" when X"4",

  "0010010" when X"5",

  "0000010" when X"6",

  "1111000" when X"7",

  "0000000" when X"8",

  "0010000" when X"9",

  "1111111" when others;


end Behavioral;

支持(0中立(0反對(0單帖管理 | 引用 | 回復 回到頂部
總數 20 1 2 下一頁

返回版面帖子列表

FPGA 時鐘問題








簽名
主站蜘蛛池模板: 久草综合在线观看 | 久久午夜鲁丝片午夜精品 | 欧美手机手机在线视频一区 | 欧美精品午夜久久久伊人 | 久久久午夜精品理论片 | 国产啪精品视频网免费 | 日韩欧美一及在线播放 | 免费人成在线观看播放国产 | 99精品国产综合久久久久 | 步兵社区 | 欧美一级带 | 国产在线视频自拍 | 狠狠色丁香婷婷综合 | 一级做性色a爱片久久片 | 91国内在线| 美国一级做a一级视频 | 欧美精品久久久久久久免费观看 | 97在线免费观看视频 | 91精品视频在线播放 | 五月久久亚洲七七综合中文网 | 久久99热成人精品国产 | 亚洲视频一区二区在线观看 | a级男女性高爱潮高清试 | 亚洲国产精品大秀在线播放 | 日本午夜小视频 | 91成人国产 | 亚洲精品国产福利 | 在线播放国产一区二区三区 | 成人综合国产乱在线 | 欧美日韩高清性色生活片 | 精品视频在线观看一区二区三区 | 亚洲国产精品久久久久久 | 欧美人成在线 | 欧美色成人 | 国产大学生自拍 | 噜噜噜狠狠夜夜躁精品 | 岛国大片在线播放高清 | 欧美三级一区二区三区 | 国产精品二区三区 | 女人张开腿男人猛桶视频 | 一级毛片aaaaaa视频免费看 |